Total Ionization Dose Effects and Single-Event Effects Studies of a 0.25 μm Silicon-On-Sapphire CMOS Technology

Silicon-on-Sapphire (SOS) CMOS is an attractive technology for radiation-tolerant circuits design. It eliminates single-event latch-up and has a smaller sensitive volume for single-event upsets (SEUs) and single-event transients (SETs) compared to Bulk CMOS technology [1, 2]. However, like any Silicon-On-Insulator technology, SOS technology has back-channel leakage as part of the total ionization dose (TID) effects [3, 4]. We are exploring the applicability of a commercial SOS technology for the front-end readout ASICs in the optical link systems for the ATLAS [5] upgrade at the Large Hadron Collider [6]. This paper presents detailed studies of both the TID and single-event effects (SEE) in Peregrine’s 0.25 μm Silicon-On-Sapphire (UltraCMOS®) process. A test chip with various test structures was designed and fabricated using this technology. The chip was irradiated with a Co-60 gamma source for TID study and with a 220 MeV proton beam for SEE study, both up to a dose comparable to that in our application. Reported here are the TID and SEE results with a dose up to 100 krad. Our results show that with a grounded sapphire substrate, the overall leakage current including back-channel leakage becomes negligible; the threshold voltage variations due to radiation for NMOS and PMOS are mitigated to about 55mV and 45mV respectively. The technology also demonstrates good SEE immunity.